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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:44:39 09/26/2013 
-- Design Name: 
-- Module Name:    d_flip_flop - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity d_flip_flop is
    Port ( clock : in  STD_LOGIC;
			  reset : in  STD_LOGIC;
			  hold : in STD_LOGIC;
           input : in  STD_LOGIC;
           output : out  STD_LOGIC);
end d_flip_flop;

architecture Behavioral of d_flip_flop is
	signal state: STD_LOGIC := '0';
begin
process (clock, reset)
begin
	if reset = '1' then
		state <= '0';
	else
		if hold = '1' then
		-- do nothing
		else
			if clock = '1' and clock'event then
				if input = '1' then
					state <= not(state);
				end if;
			end if;
		end if;
	end if;
end process;
output <= state;
end Behavioral;

